Tender Details
Tender Title / Description
| Tender Title | SUPPLY AND COMMISSIONING OF CAD LAB |
|---|---|
| Tender Description | advancecmoslayoutdesign &simulationtool(microwindlatestversion)specificationadvance cmos layout design & simulation tool software must be perpetual in nature. library based schematic editor with facility to createsymbols. library of various digital models like gates, registers,devices, etc. both conventional pattern-based logic simulation andintuitive on-screen mouse-driven simulation. supports hierarchical logic design with built-in extractorwhich generates a spice netlist from the schematicdiagram (compatible with pspice and winspice). generation of verilog description of the schematic forlayout generation. mos level schematic support. fault analysis tool at the gate level of digital circuits.faults: stuck-1, stuck-at-0. immediate access to symbol properties of models likedelay, fanout. models and assembly support for 8051 and pic 16f84with facility to simulate with external circuits. sub-micron, deep-submicron, nanoscale technologysupport. facility to list delays of path |
| Comments | advancecmoslayoutdesign &simulationtool(microwindlatestversion)specificationadvance cmos layout design & simulation tool software must be perpetual in nature. library based schematic editor with facility to createsymbols. library of various digital models like gates, registers,devices, etc. both conventional pattern-based logic simulation andintuitive on-screen mouse-driven simulation. supports hierarchical logic design with built-in extractorwhich generates a spice netlist from the schematicdiagram (compatible with pspice and winspice). generation of verilog description of the schematic forlayout generation. mos level schematic support. fault analysis tool at the gate level of digital circuits.faults: stuck-1, stuck-at-0. immediate access to symbol properties of models likedelay, fanout. models and assembly support for 8051 and pic 16f84with facility to simulate with external circuits. sub-micron, deep-submicron, nanoscale technologysupport. facility to list delays of path |
Important Dates
| Published Date | |
|---|---|
| Due Date | 06 Dec 2018 00:00:00 |
Estimate and EMD
| Estimated Value | 15.0 Lakh |
|---|---|
| EMD | 0 INR |
| Processing Fee | 0 INR |