Tender Details
Tender Title / Description
| Tender Title | Rate Contract for Selection of Truechip Training Partner Open Tender |
|---|---|
| Tender Description | Global Certification Courses Certified VLSI Design and Verification Engineer - 240 Hrs Advanced Digital System Design with Verilog HDL - 150 Hrs ASIC Verification using System Verilog and UVM - 180 Hrs Courses for Credit (Instructor Based Online + Selfpaced) Digital Systems Design using Verilog - 40 Hrs Verification using System Verilog - 40 Hrs TCL Scripting for VLSI Design and Automation - 40 Hrs Courses for Workshops Truechip Workshop - Half Day Truechip Workshop - Full Day |
| Comments | Global Certification Courses Certified VLSI Design and Verification Engineer - 240 Hrs Advanced Digital System Design with Verilog HDL - 150 Hrs ASIC Verification using System Verilog and UVM - 180 Hrs Courses for Credit (Instructor Based Online + Selfpaced) Digital Systems Design using Verilog - 40 Hrs Verification using System Verilog - 40 Hrs TCL Scripting for VLSI Design and Automation - 40 Hrs Courses for Workshops Truechip Workshop - Half Day Truechip Workshop - Full Day |
Important Dates
| Published Date | |
|---|---|
| Due Date | 29 Jul 2026 15:00:00 |
| Tender Open Date |
Estimate and EMD
| Estimated Value | 1.95 Crore |
|---|---|
| EMD | 200000 INR |
| Processing Fee | 2000 INR |